Designing a CPU model: from a pseudo-formal document to fast code

For validating low level embedded software, engineers use simulators that take the real binary as input. Like the real hardware, these full-system simulators are organized as a set of components. The main component is the CPU simulator (ISS), because it is the usual bottleneck for the simulation speed, and its development is a long and repetitive task. Previous work showed that an ISS can be generated from an Architecture Description Language (ADL). In the work reported in this paper, we generate a CPU simulator directly from the pseudo-formal descriptions of the reference manual. For each instruction, we extract the information describing its behavior, its binary encoding, and its assembly syntax. Next, after automatically applying many optimizations on the extracted information, we generate a SystemC/TLM ISS. We also generate tests for the decoder and a formal specification in Coq. Experiments show that the generated ISS is as fast and stable as our previous hand-written ISS.Comment: 3rd Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (2011

TLM.open: a SystemC/TLM Front-end for the CADP Verification Toolbox

Extended abstract for SBDCES workshop (http://unit.aist.go.jp/cvs/workshop/SBDCES.html)SystemC/TLM models allow the simulation of the embedded software before the hardware RTL descriptions are available, and are used as golden models for hardware verification. The verifi- cation of the SystemC/TLM models is an important issue, since a error in the model can mislead the system designers, or reveal an error in the specification. The OSCI provides an open-source simulator for SystemC/TLM but no tools for formal verification. In order to apply model checking to a SystemC/TLM program, the usual approach relies on the translation of the SystemC/TLM code to a formal language for which a model checker is available. We propose another approach that suppress the error-prone translation effort. Given a SystemC/TLM program, we execute the transitions using g++ and the OSCI library, and we ask the user to provide additional functions to store the current program state. These additional functions represent generally less than 20% of the size of the origianl model, and allows to apply all CADP tools to the SystemC/TLM program itself

Modeling Power Consumption and Temperature in TLM Models

International audienceMany techniques and tools exist to estimate the power consumption and the temperature map of a chip. These tools help the hardware designers develop power efficient chips in the presence of temperature constraints. For this task, the application can be ignored or at least abstracted by some high level scenarios; at this stage, the actual embedded software is generally not available yet. However, after the hardware is defined, the embedded software can still have a significant influence on the power consumption; i.e., two implementations of the same application can consume more or less power. Moreover, the actual software powe

Automatic Generation of Schedulings for Improving the Test Coverage of Systems-on-a-Chip

International audienceSystemC is becoming a de-facto standard for the early simulation of Systems-on-a-chip (SoCs). It is a parallel language with a scheduler. Testing a SoC written in SystemC implies that we execute it, for some well chosen data. We are bound to use a particular deterministic implementation of the scheduler, whose specification is non-deterministic. Consequently, we may fail to discover bugs that would have appeared using another valid implementation of the scheduler. Current methods for testings SoCs concentrate on the generation of the inputs, and do not address this problem at all. We assume that the selection of relevant data is already done, and we generate several schedulings allowed by the scheduler specification. We use dynamic partial-order reduction techniques to avoid the generation of two schedulings that have the same effect on the system's behavior. Exploring alternative schedulings during testing is a way of guaranteeing that the SoC description, and in particular the embedded software, is scheduler-independent, hence more robust. The technique extends to the exploration of other non-fully specified aspects of SoC descriptions, like timing

Fast and Accurate TLM Simulations using Temporal Decoupling for FIFO-based Communications

International audienceUntimed models of large embedded systems, generally written using SystemC/TLM, allow the software team to start simulations before the RTL description is available, and then provide a golden reference model to the verification team. For those two purposes, only a correct functional behavior is required, but users are asking more and more for timing estimations early in the design flow. Because companies cannot afford to maintain two simulators for the same chip, only local modifications of the untimed model are considered. A known approach is to add timing annotations into the code and to reduce the number of costly context switches using temporal decoupling, meaning that a process can go ahead of the simulation time before synchronizing again. Our current goal is to apply temporal decoupling to the TLM platform of a many-core SoC dedicated to high performance computing. Part of this SoC communicates using classic memory-mapped buses, but it can be extended with hardware accelerators communicating using FIFOs. Whereas temporal decoupling for memory-based transactions has been widely studied, FIFO-based communications raise issues that have not been addressed before. In this paper, we provide an efficient solution to combine temporal decoupling and FIFO-based communications

TLM.open: a SystemC/TLM Frontend for the CADP Verification Toolbox

SystemC/TLM models, which are C++ programs, allow the simulation of embedded software before hardware low-level descriptions are available and are used as golden models for hardware verification. The verification of the SystemC/TLM models is an important issue since an error in the model can mislead the system designers or reveal an error in the specifications. An open-source simulator for SystemC/TLM is provided but there are no tools for formal verification.In order to apply model checking to a SystemC/TLM model, a semantics for standard C++ code and for specific SystemC/TLM features must be provided. The usual approach relies on the translation of the SystemC/TLM code into a formal language for which a model checker is available.We propose another approach that suppresses the error-prone translation effort. Given a SystemC/TLM program, the transitions are obtained by executing the original code using g++ and an extended SystemC library, and we ask the user to provide additional functions to store the current model state. These additional functions generally represent less than 20% of the size of the original model, and allow it to apply all CADP verification tools to the SystemC/TLM model itself.</p

Validation de modèles de systèmes sur puce en présence d'ordonnancements indéterministes et de temps imprécis

This work deals with the validation of System-on-a-Chip models at the transaction level (TLM). These models are used for the development of embedded software. Hardware is highly parallel but the simulator runs on a single processor. The main parallel entities of hardware (processors, DMA, bus arbiter, ...) are modeled in TLM by asynchronous processes, which have to be scheduled at simulation time. The specification of this scheduling is non-deterministic in order to represent the physical parallelism faithfully.This induces a problem for validation by simulations: we have to cover the set of valid schedulings in addition to the set of data. Indeed, a deterministic scheduler will miss some bugs. Random schedulings will show more possible behaviors but the coverage is still uncertain. The valid schedulings of a real model are too numerous to try them all.We present a solution to effectively cover the set of schedulings. Our solution is based on dynamic partial order reduction. The idea is to look at the actions performed by the processes, in order to guess whether a change in their order (as what would be produced by distinct scheduler choices) could affect the final state. Successive iterations eventually give a complete scheduling set, which guarantees the detection of all local errors and deadlocks for a fixed data set.In order to model the still unknown timing of hardware, developers add loose timings (bounded delays) in their models. Consequently, for validation by simulations, we have to cover the set of valid timings too. We present an extension to dynamic partial order reduction to solve this problem. The new algorithm and its prototype generate a set of valid timings, such that, again, all local errors and deadlocks for a fixed data set are detected.At last, we study the parallelization of the SystemC simulator in order to take advantage of multiprocessor machines. We have to respect the SystemC specification and the special features of TLM.Ces travaux portent sur la validation de modèles de systèmes sur puce (SoC) au niveau transactionnel (TLM). Ces modèles servent notamment au développement du logiciel embarqué. Le matériel est intrinsèquement parallèle mais le simulateur utilise un seul processeur. Les principales entités parallèles du matériel (processeurs, DMA, arbitres de bus, ...) sont représentées en TLM par des processus asynchrones, qui doivent être ordonnancés lors des simulations. Cet ordonnancement est indéterministe afin de mieux représenter le parallélisme physique.Cela pose un problème pour la validation par simulations : il faut couvrir l'espace des ordonnancements en plus de celui des données. En effet, un ordonnanceur déterministe peut cacher des erreurs, car il ne montre qu'un comportement parmi d'autres. Des ordonnancements aléatoires permettent d'observer plus de comportements mais la couverture est incertaine. Un parcours exhaustif de tous les ordonnancements serait beaucoup trop long pour des tests réels.Nous présentons une solution pour couvrir efficacement l'espace des ordonnancements. Celle-ci est basée sur de la réduction d'ordre partiel dynamique. L'idée est d'observer l'influence de l'ordonnancement sur les communications entre processus, pour générer dynamiquement de nouveaux ordonnancements, menant très probablement à des états finaux différents. En itérant sur chaque nouvel ordonnancement, nous obtenons un jeu complet d'ordonnancements, qui garantit la détection, pour un jeu fixé de données, de toutes les erreurs locales et de tous les inter-blocages.Toujours avec l'objectif d'une meilleure représentativité du matériel, les développeurs ont ajouté du temps imprécis à leurs modèles TLM, sous forme de délais bornés. Pour la validation par simulations, cela oblige à couvrir aussi l'espace des temporisations. Nous présentons une extension à la réduction d'ordre partiel dynamique pour résoudre ce problème. Le nouvel algorithme et son prototype retournent un ensemble de jeux de durées, qui garantit de nouveau la détection complète des erreurs locales et inter-blocages pour des données fixées.Enfin, nous étudions comment paralléliser le simulateur SystemC afin de profiter des machines multiprocesseurs, tout en respectant la spécification de SystemC et les particularités des modèles TLM

Validation de modèles de systèmes sur puce en présence d'ordonnancements indéterministes et de temps imprécis

This work deals with the validation of System-on-a-Chip models at the transaction level (TLM). These models are used for the development of embedded software. Hardware is highly parallel but the simulator runs on a single processor. The main parallel entities of hardware (processors, DMA, bus arbiter, ...) are modeled in TLM by asynchronous processes, which have to be scheduled at simulation time. The specification of this scheduling is non-deterministic in order to represent the physical parallelism faithfully.This induces a problem for validation by simulations: we have to cover the set of valid schedulings in addition to the set of data. Indeed, a deterministic scheduler will miss some bugs. Random schedulings will show more possible behaviors but the coverage is still uncertain. The valid schedulings of a real model are too numerous to try them all.We present a solution to effectively cover the set of schedulings. Our solution is based on dynamic partial order reduction. The idea is to look at the actions performed by the processes, in order to guess whether a change in their order (as what would be produced by distinct scheduler choices) could affect the final state. Successive iterations eventually give a complete scheduling set, which guarantees the detection of all local errors and deadlocks for a fixed data set.In order to model the still unknown timing of hardware, developers add loose timings (bounded delays) in their models. Consequently, for validation by simulations, we have to cover the set of valid timings too. We present an extension to dynamic partial order reduction to solve this problem. The new algorithm and its prototype generate a set of valid timings, such that, again, all local errors and deadlocks for a fixed data set are detected.At last, we study the parallelization of the SystemC simulator in order to take advantage of multiprocessor machines. We have to respect the SystemC specification and the special features of TLM.Ces travaux portent sur la validation de modèles de systèmes sur puce (SoC) au niveau transactionnel (TLM). Ces modèles servent notamment au développement du logiciel embarqué. Le matériel est intrinsèquement parallèle mais le simulateur utilise un seul processeur. Les principales entités parallèles du matériel (processeurs, DMA, arbitres de bus, ...) sont représentées en TLM par des processus asynchrones, qui doivent être ordonnancés lors des simulations. Cet ordonnancement est indéterministe afin de mieux représenter le parallélisme physique.Cela pose un problème pour la validation par simulations : il faut couvrir l'espace des ordonnancements en plus de celui des données. En effet, un ordonnanceur déterministe peut cacher des erreurs, car il ne montre qu'un comportement parmi d'autres. Des ordonnancements aléatoires permettent d'observer plus de comportements mais la couverture est incertaine. Un parcours exhaustif de tous les ordonnancements serait beaucoup trop long pour des tests réels.Nous présentons une solution pour couvrir efficacement l'espace des ordonnancements. Celle-ci est basée sur de la réduction d'ordre partiel dynamique. L'idée est d'observer l'influence de l'ordonnancement sur les communications entre processus, pour générer dynamiquement de nouveaux ordonnancements, menant très probablement à des états finaux différents. En itérant sur chaque nouvel ordonnancement, nous obtenons un jeu complet d'ordonnancements, qui garantit la détection, pour un jeu fixé de données, de toutes les erreurs locales et de tous les inter-blocages.Toujours avec l'objectif d'une meilleure représentativité du matériel, les développeurs ont ajouté du temps imprécis à leurs modèles TLM, sous forme de délais bornés. Pour la validation par simulations, cela oblige à couvrir aussi l'espace des temporisations. Nous présentons une extension à la réduction d'ordre partiel dynamique pour résoudre ce problème. Le nouvel algorithme et son prototype retournent un ensemble de jeux de durées, qui garantit de nouveau la détection complète des erreurs locales et inter-blocages pour des données fixées.Enfin, nous étudions comment paralléliser le simulateur SystemC afin de profiter des machines multiprocesseurs, tout en respectant la spécification de SystemC et les particularités des modèles TLM

TLM.open: a SystemC/TLM Front-end for the CADP Verification Toolbox

Extended abstract for SBDCES workshop (http://unit.aist.go.jp/cvs/workshop/SBDCES.html)SystemC/TLM models allow the simulation of the embedded software before the hardware RTL descriptions are available, and are used as golden models for hardware verification. The verifi- cation of the SystemC/TLM models is an important issue, since a error in the model can mislead the system designers, or reveal an error in the specification. The OSCI provides an open-source simulator for SystemC/TLM but no tools for formal verification. In order to apply model checking to a SystemC/TLM program, the usual approach relies on the translation of the SystemC/TLM code to a formal language for which a model checker is available. We propose another approach that suppress the error-prone translation effort. Given a SystemC/TLM program, we execute the transitions using g++ and the OSCI library, and we ask the user to provide additional functions to store the current program state. These additional functions represent generally less than 20% of the size of the origianl model, and allows to apply all CADP tools to the SystemC/TLM program itself

Validation de modèles de systèmes sur puce en présence d ordonnancements indéterministes et de temps imprécis@

Nous étudions la validation par simulations de modèles SystemC- TLM de systèmes-sur-puce, servant au développement du logiciel embarqué. Les entités parallèles du matériel sont modélisées par des processus asynchrones, dont la politique d'ordonnancement est indéterministe afin de mieux représenter le parallélisme physique. Nous devons couvrir l'espace des ordonnancements en plus de celui des données, puisque le résultat d'une simulation peut dépendre de l'ordonnancement. Nous présentons une adaptation de la réduction d'ordre par dynamique pour couvrir efficacement l'espace des ordonnancements, ainsi qu'une extension pour les systèmes temporisés avec délais bornés. L'idée est d'observer les communications entre processus, pour générer dynamiquement de nouveaux entrelacements pertinents. Cet algorithme et le prototype réalisé retournent un ensemble d'ordonnancements et de jeux de durées, qui garantit la détection complète des erreurs locales et inter-blocages pour des données fixées.We study the validation by simulations of System-on-a-Chip models, written in SystemC-TLM. These models al used for the development of embedded software. Parallel entities of hardware are modeled by asynchronous processes, whose scheduling policy is non-deterministic in order to represent the physical parallelism faithfully. We have to cover the set of valid interleavings in addition to the set of data, since the result of a simulation may depend on the scheduling. We present an adaptation of dynamic partial order reduction to effectively cover the scheduling set, and an extension for timed models with bounded delays. The idea is to look at communications between processes, in order to guess whether a change in their order (as what would be produced by distinct scheduler choices) could affect the final state. This algorithm and its implementation return a complete schedulin and timing set, which guarantees the detection of aIl local errors and deadlocks for a fixed data set.GRENOBLE1-BU Sciences (384212103) / SudocSudocFranceF